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Card-based Cryptography Meets Formal Verification
secure multiparty computation card-based cryptography formal verification
2019/9/17
Card-based cryptography provides simple and practicable protocols for performing secure multi-party computation (MPC) with just a deck of cards. For the sake of simplicity, this is often done using ca...
Formal Verification of a Constant-Time Preserving C Compiler
Compilation Formal verification Constant-time security
2019/8/19
Timing side-channels are arguably one of the main sources of vulnerabilities in cryptographic implementations. One effective mitigation against timing side-channels is to write programs that do not pe...
Sharing Independence & Relabeling: Efficient Formal Verification of Higher-Order Masking
masking formal verification domain-oriented masking
2018/11/2
The efficient verification of the security of masked hardware implementations is an important issue that hinders the development and deployment of randomness-efficient masking techniques. At EUROCRYPT...
Formal Verification of Masked Hardware Implementations in the Presence of Glitches
masking formal verification threshold implementations
2017/9/25
Masking provides a high level of resistance against side-channel analysis. However, in practice there are many possible pitfalls when masking schemes are applied, and implementation flaws are easily o...
Formal Verification of Side-channel Countermeasures via Elementary Circuit Transformations
Side-channel countermeasures masking formal verification
2017/9/14
We describe a technique to formally verify the security of masked implementations against side-channel attacks, based on elementary circuit transformations. We describe two complementary approaches: a...
Formal verification of a software countermeasure against instruction skip attacks
instruction skip countermeasure
2014/3/6
Fault attacks against embedded circuits enabled to define many new attack paths against secure circuits. Every attack path relies on a specific fault model which defines the type of faults that the at...
FBDVerifier: Interactive and Visual Analysis of Counterexample in Formal Verification of Function Block Diagram
Function Block Diagram Formal Verification Counter-example Visualization Verilog Translation Programmable Logic Controller Model Checking
2014/3/11
Model checking is often applied to verify safety-critical software implemented in programmable logic controller (PLC) language such as a function block diagram (FBD). Counter-examples generated by a m...